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octal, 14-bit, 125 msps, serial lvds, 1.8 v analog-to-digital converter data sheet ad9681 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power 8 adc channels integrated into 1 package 110 mw per channel at 125 msps with scalable power options snr: 74 dbfs (to nyquist); sfdr: 90 dbc (to nyquist) dnl: 0.8 lsb (typical); inl: 1.2 lsb (typical) crosstalk, worst adjacent channel, 70 mhz, ?1 dbfs: ?83 db typical serial lvds (ansi-644, default) low power, reduced signal option (similar to ieee 1596.3) data and frame clock outputs 650 mhz full power analog bandwidth 2 v p-p input voltage range 1.8 v supply operation serial port control flexible bit orientation built-in and custom digital test pattern generation programmable clock and data alignment power-down and standby modes applications medical imaging communications receivers multichannel data acquisition general description the ad9681 is an octal, 14-bit, 125 msps analog-to-digital converter (adc) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. the device operates at a conversion rate of up to 125 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and an lvpecl-/ cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the ad9681 automatically multiplies the sample rate clock for the appropriate lvds serial data rate. data clock outputs (dco1, dco2) for capturing data on the output and frame clock outputs (fco1, fco2) for signaling a new output byte are provided. individual channel power-down is supported, and the device typically consumes less than 2 mw when all channels are disabled. simplified functional block diagram 11537-200 14 pipeline adc digital serializer vin?a1 vin+a1 14 pipeline adc digital serializer vin?a2 vin+a2 fco?1, fco?2 fco+1, fco+2 dco?1, dco?2 dco+1, dco+2 d1?d2 d1+d2 14 pipeline adc digital serializer vin?d1 vin+d1 14 pipeline adc digital serializer vin?d2 vin+d2 avdd pdwn drvdd sense gnd vref ref select 1v vcm1, vcm2 sync clk+ clk? clock management csb1, csb2 rbias1, rbias2 sdio/olm sclk/dtp serial port interface ad9681 serial lvds d0?d1 d0+d1 serial lvds d1?d1 d1+d1 serial lvds d0?d2 d0+d2 serial lvds serial lvds d0?a1 d0+a1 serial lvds d1?a1 d1+a1 serial lvds d0?a2 d0+a2 serial lvds d1?a2 d1+a2 figure 1. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (spi). the ad9681 is available in an rohs-compliant, 144-ball csp- bga. it is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. small footprint. eight adcs are contained in a small, 10 mm 10 mm package. 2. low power. the device dissipates 110 mw per channel at 125 msps with scalable power options. 3. ease of use. data clock outputs (dco1, dco2) operate at frequencies of up to 500 mhz and support double data rate (ddr) operation. 4. user flexibility. spi control offers a wide range of flexible features to meet specific system requirements.
ad9681 data sheet rev. a | page 2 of 40 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? simplified functional block diagram ........................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications ..................................................................................... 4 ? dc specifications ......................................................................... 4 ? ac specifications .......................................................................... 5 ? digital specifications ................................................................... 6 ? switching specifications .............................................................. 7 ? timing specifications .................................................................. 8 ? absolute maximum ratings .......................................................... 12 ? thermal characteristics ............................................................ 12 ? esd caution ................................................................................ 12 ? pin configuration and function descriptions ........................... 13 ? typical performance characteristics ........................................... 15 ? equivalent circuits ......................................................................... 18 ? theory of operation ...................................................................... 19 ? analog input considerations .................................................... 19 ? voltage reference ....................................................................... 20 ? clock input considerations ...................................................... 21 ? power dissipation and power-down mode ........................... 23 ? digital outputs and timing ..................................................... 24 ? output test modes ..................................................................... 27 ? serial port interface (spi) .............................................................. 28 ? configuration using the spi ..................................................... 28 ? hardware interface ..................................................................... 29 ? configuration without the spi ................................................ 29 ? spi accessible features .............................................................. 29 ? memory map .................................................................................. 30 ? reading the memory map register table ............................... 30 ? memory map register table ..................................................... 31 ? memory map register descriptions ........................................ 34 ? applications information .............................................................. 37 ? design guidelines ...................................................................... 37 ? power and ground recommendations ................................... 37 ? board layout considerations ................................................... 37 ? clock stability considerations ................................................. 38 ? reference decoupling ................................................................ 38 ? spi port ........................................................................................ 38 ? outline dimensions ....................................................................... 39 ? ordering guide .......................................................................... 39 ? revision history 12/13rev. 0 to rev. a changes to ordering guide .......................................................... 39 11/13revision 0: initial version
data sheet ad9681 rev. a | page 3 of 40 functional block diagram serial lvds d0?a1 d0+a1 serial lvds d1?a1 d1+a1 serial lvds d0?a2 d0+a2 serial lvds d1?a2 d1+a2 serial lvds d0?b1 d0+b1 serial lvds d1?b1 d1+b1 serial lvds d0?b2 d0+b2 serial lvds d1?b2 d1+b2 14 pipeline adc digital serializer vin?a1 vin+a1 14 pipeline adc digital serializer vin?a2 vin+a2 14 pipeline adc digital serializer vin?b1 vin+b1 14 pipeline adc digital serializer vin?b2 vin+b2 fco?1, fco?2 fco+1, fco+2 dco?1, dco?2 dco+1, dco+2 serial lvds d0?c1 d0+c1 serial lvds d1?c1 d1+c1 serial lvds d0?c2 d0+c2 serial lvds d1?c2 d1+c2 serial lvds d0?d1 d0+d1 serial lvds d1?d1 d1+d1 serial lvds d0?d2 d0+d2 serial lvds d1?d2 d1+d2 14 pipeline adc digital serializer vin?c1 vin+c1 14 pipeline adc digital serializer vin?c2 vin+c2 14 pipeline adc digital serializer vin?d1 vin+d1 14 pipeline adc digital serializer vin?d2 vin+d2 a vdd pdwn drvdd sense gnd vref rbias1, rbias2 ref select 1v vcm1, vcm2 sync clk+ clk? clock management csb1, csb2 sdio/olm sclk/dtp serial port interface ad9681 11537-001 figure 2.
ad9681 data sheet rev. a | page 4 of 40 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 1. parameter 1 temp min typ max unit resolution 14 bits accuracy no missing codes full guaranteed offset error full ?0.23 +0.21 +0.62 % fsr offset matching full 0 0.24 0.7 % fsr gain error full ?8.0 ?3.1 +1.7 % fsr gain matching full 0 1.8 6.0 % fsr differential nonlinearity (dnl) full ?0.92 0.8 +1.75 lsb integral nonlinearity (inl) full ?4.0 1.2 +4.0 lsb temperature drift offset error full ?4 ppm/c gain error full 38 ppm/c internal voltage reference output voltage (1 v mode) full 0.98 1.0 1.02 v load regulation at 1.0 ma (v ref = 1 v) 25c 3 mv input resistance full 7.5 k input-referred noise v ref = 1.0 v 25c 0.99 lsb rms analog inputs differential input voltage (v ref = 1 v) full 2 v p-p common-mode voltage full 0.5 0.9 1.3 v differential input resistance full 5.2 k differential input capacitance full 3.5 pf power supply avdd full 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 v i avdd full 368 423 ma i drvdd (ansi-644 mode) full 120 126 ma i drvdd (reduced range mode) 25c 90 ma total power consumption total power dissipation (eight channels, including output drivers ansi-644 mode) full 879 988 mw total power dissipation (eight channels, including output drivers reduced range mode) 25c 825 mw power-down dissipation 25c 2 mw standby dissipation 2 25c 485 mw 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for information about how these tests were completed. 2 controlled via the spi.
data sheet ad9681 rev. a | page 5 of 40 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 2. parameter 1 temp min typ max unit signal-to-noise ratio (snr) f in = 9.7 mhz 25c 74.8 dbfs f in = 19.7 mhz 25c 74.7 dbfs f in = 69.5 mhz full 72.6 73.9 dbfs f in = 139.5 mhz 25c 71.5 dbfs f in = 201 mhz 25c 69.6 dbfs f in = 301 mhz 25c 66.6 dbfs signal-to-noise and distortion ratio (sinad) f in = 9.7 mhz 25c 74.7 dbfs f in = 19.7 mhz 25c 74.7 dbfs f in = 69.5 mhz full 72.3 73.8 dbfs f in = 139.5 mhz 25c 71.4 dbfs f in = 201 mhz 25c 69.3 dbfs f in = 301 mhz 25c 65.8 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 12.1 bits f in = 19.7 mhz 25c 12.1 bits f in = 69.5 mhz full 11.7 12.0 bits f in = 139.5 mhz 25c 11.6 bits f in = 201 mhz 25c 11.2 bits f in = 301 mhz 25c 10.6 bits spurious-free dynamic range (sfdr) f in = 9.7 mhz 25c 94 dbc f in = 19.7 mhz 25c 94 dbc f in = 69.5 mhz full 81 90 dbc f in = 139.5 mhz 25c 87 dbc f in = 201 mhz 25c 83 dbc f in = 301 mhz 25c 73 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ?94 dbc f in = 19.7 mhz 25c ?94 dbc f in = 69.5 mhz full ?90 ?81 dbc f in = 139.5 mhz 25c ?87 dbc f in = 201 mhz 25c ?83 dbc f in = 301 mhz 25c ?73 dbc worst other (excluding second or third) f in = 9.7 mhz 25c ?98 dbc f in = 19.7 mhz 25c ?94 dbc f in = 69.5 mhz full ?96 ?84 dbc f in = 139.5 mhz 25c ?90 dbc f in = 201 mhz 25c ?85 dbc f in = 301 mhz 25c ?75 dbc two-tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 70 mhz, f in2 = 72.5 mhz 25c 94 dbc crosstalk, worst adjacent channel 2 25c ?83 db crosstalk, worst adjacent channel overrange condition 3 25c ?79 db analog input bandwidth, full power 25c 650 mhz 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 crosstalk is measured at 70 mhz, with ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 3 overrange condition is defined as 3 db above input full scale.
ad9681 data sheet rev. a | page 6 of 40 digital specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 3. parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p-p input voltage range full gnd ? 0.2 avdd + 0.2 v input common-mode voltage full 0.9 v input resistance (differential) 25c 15 k input capacitance 25c 4 pf logic inputs (pdwn, sync, sclk) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k input capacitance 25c 2 pf logic inputs (csb1, csb2) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 2 pf logic input (sdio) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d0xx, d1xx), ansi-644 logic compliance lvds differential output voltage (v od ) full 290 345 400 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) twos complement digital outputs (d0xx, d1xx), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 160 200 230 mv output offset voltage (v os ) full 1.15 1.25 1.35 v output coding (default) twos complement 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 specified for lvds and lvpecl only. 3 specified for 13 sdio/olm pins sharing the same connection.
data sheet ad9681 rev. a | page 7 of 40 switching specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, a in = ?1.0 dbfs, unless otherwise noted. table 4. parameter 1, 2 symbol temp min typ max unit clock 3 input clock rate full 10 1000 mhz conversion rate full 10 125 msps clock pulse width high t eh full 4.00 ns clock pulse width low t el full 4.00 ns output parameters 3 propagation delay t pd full 1.5 2.3 3.1 ns rise time (20% to 80%) t r full 300 ps fall time (20% to 80%) t f full 300 ps fco1, fco2 propagation delay t fco full 1.5 2.3 3.1 ns dco1, dco2 propagation delay 4 t cpd full t fco + (t sample /16) ns dco1, dco2 to data delay 4 t data full (t sample /16) ? 300 (t sample /16) (t sample /16) + 300 ps dco1, dco2 to fco1, fco2 delay 4 t frame full (t sample /16) ? 300 (t sample /16) (t sample /16) + 300 ps lane delay t ld 90 ps data to data skew t data-max ? t data-min full 50 200 ps wake-up time (standby) 25c 250 ns wake-up time (power-down) 5 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay t a 25c 1 ns aperture uncertainty (jitter) t j 25c 135 fs rms out-of-range recovery time 25c 1 clock cycles 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr-4 material. 3 adjustable using the spi. the conversion rate is the clock rate after the divider. 4 t sample /16 is based on the number of bits in two lvds data lanes. t sample = 1/f sample . 5 wake-up time is defined as the time required to return to normal operation from power-down mode.
ad9681 data sheet rev. a | page 8 of 40 timing specifications table 5. parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 0.24 ns typ t hsync sync to rising edge of clk+ hold time 0.40 ns typ spi timing requirements see figure 53 t ds setup time between the data and th e rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb1/csb2 and sclk 2 ns min t h hold time between csb1/csb2 and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 53) 10 ns min t dis_sdio time required for the sdio pin to switch fr om an output to an input relative to the sclk rising edge (not shown in figure 53) 10 ns min timing diagrams refer to the memory map register descriptions section and tale 21 for spi register setting of output modes d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 bytewise mode fco+1, fco+2 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 dco?1, dco?2 dco+1, dco+2 dco+1, dco+2 clk+ vinx1, vinx2 clk? dco?1, dco?2 fco+1, fco+2 bitwise mode sdr ddr msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 11537-003 figure 3. 16-bit ddr/sdr, two-lane, 1 frame mode (default)
data sheet ad9681 rev. a | page 9 of 40 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 bytewise mode fco+1, fco+2 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 dco?1, dco?2 dco+1, dco+2 dco+1, dco+2 clk+ clk? dco?1, dco?2 fco+1, fco+2 bitwise mode sdr ddr d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx1, vinx2 t a n ? 1 n n + 1 11537-004 figure 4. 12-bit ddr/sdr, two-lane, 1 frame mode d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 fco+1, fco+2 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 dco?1, dco?2 dco+1, dco+2 dco+1, dco+2 clk+ vinx1, vinx2 clk? dco?1, dco?2 fco+1, fco+2 bytewise mode bitwise mode sdr ddr msb n ? 17 d12 n ? 17 d11 n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 msb n ? 16 d12 n ? 16 d11 n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 0 n ? 16 0 n ? 16 msb n ? 17 d11 n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 0 n ? 17 msb n ? 16 d11 n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 0 n ? 16 d12 n ? 17 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 0 n ? 17 d12 n ? 16 d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 0 n ? 16 t a t data t ld t eh t fco t frame t pd t cpd t el n ? 1 n n + 1 11537-005 figure 5. 16-bit ddr/sdr, two-lane, 2 frame mode
ad9681 data sheet rev. a | page 10 of 40 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 bytewise mode fco+1, fco+2 d0?a1 d0+a1 d1?a1 d1+a1 fco?1, fco?2 dco?1, dco?2 dco+1, dco+2 dco+1, dco+2 clk+ clk? dco?1, dco?2 fco+1, fco+2 bitwise mode sdr ddr d10 n ? 16 d08 n ? 16 d06 n ? 16 d04 n ? 16 d02 n ? 16 lsb n ? 16 d10 n ? 17 d08 n ? 17 d06 n ? 17 d04 n ? 17 d02 n ? 17 lsb n ? 17 msb n ? 16 d09 n ? 16 d07 n ? 16 d05 n ? 16 d03 n ? 16 d01 n ? 16 msb n ? 17 d09 n ? 17 d07 n ? 17 d05 n ? 17 d03 n ? 17 d01 n ? 17 d05 n ? 16 d04 n ? 16 d03 n ? 16 d02 n ? 16 d01 n ? 16 lsb n ? 16 d05 n ? 17 d04 n ? 17 d03 n ? 17 d02 n ? 17 d01 n ? 17 lsb n ? 17 msb n ? 16 d10 n ? 16 d09 n ? 16 d08 n ? 16 d07 n ? 16 d06 n ? 16 msb n ? 17 d10 n ? 17 d09 n ? 17 d08 n ? 17 d07 n ? 17 d06 n ? 17 t eh t cpd t frame t fco t pd t data t ld t el vinx1, vinx2 t a n ? 1 n n + 1 11537-006 figure 6. 12-bit ddr/sdr, two-lane, 2 frame mode d0?x d0+x fco?1, fco?2 dco+1, dco+2 clk+ vinx1, vinx2 clk? dco?1, dco?2 fco+1, fco+2 d12 n ? 17 msb n ? 17 d11 n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 lsb n ? 17 0 n ? 17 0 n ? 17 msb n ? 16 d14 n ? 16 d13 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 11537-002 figure 7. wordwise ddr, one-lane , 1 frame, 16-bit output mode
data sheet ad9681 rev. a | page 11 of 40 d0?x d0+x fco?1, fco?2 dco+1, dco+2 clk+ vinx1, vinx2 clk? dco?1, dco?2 fco+1, fco+2 d10 n ? 17 msb n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 msb n ? 16 d10 n ? 16 t a t data t eh t fco t frame t pd t cpd t el n ? 1 n 11537-082 figure 8. wordwise ddr, one-lane , 1 frame, 12-bit output mode s ync clk+ t hsync t ssync 11537-079 figure 9. sync input timing requirements
ad9681 data sheet rev. a | page 12 of 40 absolute maximum ratings table 6. parameter rating electrical avdd to gnd ?0.3 v to +2.0 v drvdd to gnd ?0.3 v to +2.0 v digital outputs (d0xx, d1xx, dco1, dco2, fco1, fco2) to gnd ?0.3 v to +2.0 v clk+, clk? to gnd ?0.3 v to +2.0 v vinx1, vinx2 to gnd ?0.3 v to +2.0 v sclk/dtp, sdio/olm, csb1, csb2 to gnd ?0.3 v to +2.0 v sync, pdwn to gnd ?0.3 v to +2.0 v rbias1, rbias2 to gnd ?0.3 v to +2.0 v vref, vcm1, vcm2, sense to gnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics typical ja is specified for a 4-layer pcb with a solid ground plane. airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . table 7. thermal resistance (simulated) package type airflow velocity (m/sec) ja 1, 2 ? jt 1, 2 unit 144-ball, 10 mm 10 mm csp-bga 0 30.2 0.13 c/w 1 per jedec 51-7, plus jede c 51-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). esd caution
data sheet ad9681 rev. a | page 13 of 40 pin configuration and fu nction descriptions vin?d1 vin+d1 nc vin?c2 nc vin?c1 nc nc vin?b2 nc vin+b1 vin?b1 nc nc nc vin+c2 nc vin+c1 nc nc vin+b2 nc nc nc vin?d2 vin+d2 sync vcm1 vcm2 vref sense rbias1 rbias2 gnd vin+a2 vin?a2 gnd gnd gnd avdd avdd avdd avdd avdd avdd gnd nc nc clk? clk+ gnd avdd gnd gnd gnd gnd avdd csb1 vin+a1 vin?a1 gnd gnd gnd avdd gnd gnd gnd gnd avdd csb2 sdio/olm sclk/dtp d1?d2 d1+d2 gnd avdd gnd gnd gnd gnd avdd pdwn d0+a1 d0?a1 d0?d2 d0+d2 gnd avdd gnd gnd gnd gnd avdd gnd d1+a1 d1?a1 d1?d1 d1+d1 gnd avdd avdd avdd avdd avdd avdd gnd d0+a2 d0?a2 d0?d1 d0+d1 drvdd drvdd gnd gnd gnd gnd drvdd drvdd d1+a2 d1?a2 d1?c2 d1+c2 d1+c1 d0+c1 fco+1 dco+1 dco+2 fco+2 d1+b2 d0+b2 d0+b1 d0?b1 d0?c2 d0+c2 d1?c1 d0?c1 fco?1 dco?1 dco?2 fco?2 d1?b2 d0?b2 d1+b1 d1?b1 a b c d e f g h j k l m 123456789101112 a d9681 top view (not to scale) 11537-009 notes 1. nc = no connect. these pins are not electrically connected to the device. however, connect these pins to board ground where possible. figure 10. pin configuration table 8. pin function descriptions pin no. mnemonic description a3, a5, a7, a8, a10, b1 to b3, b5, b7, b8, b10 to b12, d11, d12 nc no connect. these pins are not electrically connected to the device. however, connect these pins to board ground where possible. c10, d1 to d3, d10, e3, e5 to e8, f1 to f3, f5 to f8, g3, g5 to g8, h3, h5 to h8, h10, j3, j10, k5 to k8 gnd ground. d4 to d9, e4, e9, f4, f9, g4, g9, h4, h9, j4 to j9 avdd 1.8 v analog supply. k3, k4, k9, k10 drvdd 1.8 v digital output driver supply. e1, e2 clk?, clk+ input clock complement, input clock true.
ad9681 data sheet rev. a | page 14 of 40 pin no. mnemonic description g12, g11 d0?a1, d0+a1 lane 0 bank 1 digital outp ut complement, lane 0 bank 1 digital output true. h12, h11 d1?a1, d1+a1 lane 1 bank 1 digital outp ut complement, lane 1 bank 1 digital output true. j12, j11 d0?a2, d0+a2 lane 0 bank 2 digital outp ut complement, lane 0 bank 2 digital output true. k12, k11 d1?a2, d1+a2 lane 1 bank 2 digital outp ut complement, lane 1 bank 2 digital output true. l12, l11 d0?b1, d0+b1 lane 0 bank 1 digital outp ut complement, lane 0 bank 1 digital output true. m12, m11 d1?b1, d1+b1 lane 1 bank 1 digital outp ut complement, lane 1 bank 1 digital output true. m10, l10 d0?b2, d0+b2 lane 0 bank 2 digital outp ut complement, lane 0 bank 2 digital output true. m9, l9 d1?b2, d1+b2 lane 1 bank 2 digital outp ut complement, lane 1 bank 2 digital output true. m4, l4 d0?c1, d0+c1 lane 0 bank 1 digital outp ut complement, lane 0 bank 1 digital output true. m3, l3 d1?c1, d1+c1 lane 1 bank 1 digital outp ut complement, lane 1 bank 1 digital output true. m1, m2 d0?c2, d0+c2 lane 0 bank 2 digital outp ut complement, lane 0 bank 2 digital output true. l1, l2 d1?c2, d1+c2 lane 1 bank 2 digital outp ut complement, lane 1 bank 2 digital output true. k1, k2 d0?d1, d0+d1 lane 0 bank 1 digital outp ut complement, lane 0 bank 1 digital output true. j1, j2 d1?d1, d1+d1 lane 1 bank 1 digital outp ut complement, lane 1 bank 1 digital output true. h1, h2 d0?d2, d0+d2 lane 0 bank 2 digital outp ut complement, lane 0 bank 2 digital output true. g1, g2 d1?d2, d1+d2 lane 1 bank 2 digital outp ut complement, lane 1 bank 2 digital output true. m6, l6; m7, l7 dco?1, dco+1; dco?2, dco+2 data clock digital output complement, data cl ock digital output true. dco1 is used to capture d0x1/d1x1 digital output data, and dc o2 is used to capture d0x2/d1x2 digital output data. m5, l5; m8, l8 fco?1, fco+1; fco?2, fco+2 frame clock digital output complement, fram e clock digital output true. fco1 frames d0x1/d1x1 digital output data, and fco2 frames d0x2/d1x2 digital output data. f12 sclk/dtp serial clock/digital test pattern. f11 sdio/olm serial data in put/output/output lane mode. e10, f10 csb1, csb2 chip select bar. csb1 enables/disables the spi for four channels in bank 1; csb2 enables/ disables the spi for four channels in bank 2. g10 pdwn power-down. e12, e11 vin?a1, vin+a1 analog in put complement, analog input true. c12, c11 vin?a2, vin+a2 analog in put complement, analog input true. a12, a11 vin?b1, vin+b1 analog in put complement, analog input true. a9, b9 vin?b2, vin+b2 analog inp ut complement, analog input true. a6, b6 vin?c1, vin+c1 analog inp ut complement, analog input true. a4, b4 vin?c2, vin+c2 analog inp ut complement, analog input true. a1, a2 vin?d1, vin+d1 analog input complement, analog input true. c1, c2 vin?d2, vin+d2 analog input complement, analog input true. c8, c9 rbias1, rbias2 sets analog curren t bias. connect each rbiasx pin to a 10 k (1% tolerance) resistor to ground. c7 sense reference mode selection. c6 vref voltage reference input/output. c4, c5 vcm1, vcm2 analog output voltage at midsupply. sets the co mmon mode of the analog inputs, external to the adc, as shown in figure 38 and figure 39. c3 sync digital input; synchronizing input to clock divider. this pin is internally pulled to ground by a 30 k resistor.
data sheet ad9681 rev. a | page 15 of 40 typical performance characteristics 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 9.7mhz snr = 74.99dbfs sinad = 73.96dbc sfdr = 96.4dbc 11537-110 figure 11. single-tone 32k fft with f in = 9.7 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 19.7mhz snr = 74.77dbfs sinad = 73.7dbc sfdr = 94.2dbc 11537-111 figure 12. single-tone 32k fft with f in = 19.7 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 69.5mhz snr = 73.85dbfs sinad = 72.76dbc sfdr = 90dbc 11537-112 figure 13. single-tone 32k fft with f in = 69.5 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 139.5mhz snr = 71.73dbfs sinad = 70.63dbc sfdr = 87.9dbc 11537-113 figure 14. single-tone 32k fft with f in = 139.5 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 201mhz snr = 69.71dbfs sinad = 68.56dbc sfdr = 84.1dbc 11537-115 figure 15. single-tone 32k fft with f in = 201 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?1dbfs f in = 301mhz snr = 66.97dbfs sinad = 65.22dbc sfdr = 75.8dbc 11537-116 figure 16. single-tone 32k fft with f in = 301 mhz; f sample = 125 msps
ad9681 data sheet rev. a | page 16 of 40 120 ?20 ?100 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) 0 20 40 60 80 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 snr (db) sfdr (dbc) snrfs (dbfs) sfdr (dbfs) 11537-117 figure 17. snr/sfdr vs. input amplitude (a in ); f in = 9.7 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 0 102030405060 amplitude (dbfs) frequency (mhz) a in = ?7dbfs f in = 70mhz, 72.5mhz imd2 = ?100dbc imd3 = ?99.5dbc sfdr = 97.5dbc f2?f1 f1+f2 f1+2f2 2f1+f2 2f2?f1 2f1?f2 11537-118 figure 18. two-tone 32k fft with f in1 = 70.5 mhz and f in2 = 72.5 mhz; f sample = 125 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) imd3 (dbc) sfdr (dbfs) imd3 (dbfs) 11537-119 figure 19. two-tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 70.0 mhz and f in2 = 72.5 mhz; f sample = 125 msps 100 90 80 70 60 50 40 30 20 10 0 0 50 100 150 200 250 300 350 400 450 500 snr/sfdr (dbfs/dbc) input frequency (mhz) snrfs (dbfs) sfdr (dbc) 11537-120 figure 20. snr/sfdr vs. f in ; f sample = 125 msps 100 95 90 85 80 75 70 ?40 ?15 10 35 60 85 snr/sfdr (dbfs/dbc) temperature (c) snrfs (dbfs) sfdr (dbc) 11537-121 figure 21. snr/sfdr vs. temperature; f in = 9.7 mhz, f sample = 125 msps
data sheet ad9681 rev. a | page 17 of 40 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) output code 1 2000 4000 6000 8000 10000 12000 14000 16000 11537-122 figure 22. inl; f in = 9.7 mhz, f sample = 125 msps 0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 dnl (lsb) output code 1 2000 4000 6000 8000 10000 12000 14000 16000 11537-123 figure 23. dnl; f in = 9.7 mhz, f sample = 125 msps 900000 800000 700000 600000 500000 400000 300000 200000 100000 0 number of hits output code 11537-124 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 0.99 lsb rms figure 24. input referred noise histogram; f sample = 125 msps 110 105 100 95 90 85 80 75 70 65 60 snr/sfdr (dbfs/dbc) sample rate (msps) 20 130120110 1009080 70 60 5040 30 snrfs (dbfs) sfdr (dbc) 11537-126 figure 25. snr/sfdr vs. sample rate; f in = 9.7 mhz, f sample = 125 msps 110 105 100 95 90 85 80 75 70 65 60 snr/sfdr (dbfs/dbc) sample rate (msps) 20 130120110 1009080 70 60 5040 30 snrfs (dbfs) sfdr (dbc) 11537-127 figure 26. snr/sfdr vs. sample rate; f in = 70 mhz, f sample = 125 msps
ad9681 data sheet rev. a | page 18 of 40 equivalent circuits a v dd v iny1, viny2 11537-008 figure 27. equivalent analog input circuit clk+ clk? 0.9v 15k ? 10 ? 10 ? 15k ? avdd a v dd 11537-037 figure 28. equivalent clock input circuit sdio/olm avdd 400 ? 31k? 11537-036 figure 29. equivalent sdio/olm input circuit dr v dd d0?x1, d1?x1, d0?x2, d1?x2 d0+x1, d1+x1, d0+x2, d1+x2 v v v v 11537-046 figure 30. equivalent digital output circuit 350 ? avdd 30k ? sclk/dtp, sync, and pdwn 11537-012 figure 31. equivalent sclk/dtp, sync, and pdwn input circuit rbias1, rbias2 a nd vcm1, vcm2 375 ? avdd 11537-013 figure 32. equivalent rbiasx and vcmx circuit csb1, csb2 350 ? a vdd 30k ? 11537-014 figure 33. equivalent csbx input circuit vref a v dd 7.5k ? 375 ? 11537-015 figure 34. equivalent vref circuit
data sheet ad9681 rev. a | page 19 of 40 theory of operation the ad9681 is a multistage, pipelined adc. each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. the serializer transmits this converted data in a 16-bit output. the pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor dac and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input considerations the analog input to the ad9681 is a differential switched capacitor circuit designed for processing differential input signals. this circuit can support a wide common-mode range while maintaining excellent performance. by using an input common- mode voltage of midsupply, users can minimize signal dependent errors and achieve optimum performance. ss h c par c sample c sample c par vin?x1, vin?x2 h ss h v in+x1, vin+x2 h 11537-051 figure 35. switched capacitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 35). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor, in series with each input, can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. place either a differential capacitor or two single-ended capacitors on the inputs to provide a matching passive network. this configuration ultimately creates a low-pass filter at the input to limit unwanted broadband noise. see the an-742 application note , frequency domain response of switched-capacitor adcs ; the an-827 application note , a resonant approach to interfacing amplifiers to switched- capacitor adcs ; and the analog dialogue article transformer- coupled front-end for wideband a/d converters (volume 39, april 2005) for more information. in general, the precise values vary, depending on the application. input common mode the analog inputs of the ad9681 are not internally dc biased. therefore, in ac-coupled applications, the user must provide this bias externally. for optimum performance, set the device so that v cm = avdd/2. however, the device can function over a wider range with reasonable performance, as shown in figure 36. an on-chip, common-mode voltage reference is included in the design and is available at the vcmx pin. decouple the vcmx pin to ground using a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9681 , the largest available input span is 2 v p-p. 100 20 0.5 snr/sfdr (dbfs/dbc) v cm (v) 30 40 50 60 70 80 90 0.7 0.9 1.1 1.3 snr (dbfs) sfdr (dbc) 11537-052 figure 36. snr/sfdr vs. common-mode voltage; f in = 9.7 mhz, f sample = 125 msps
ad9681 data sheet rev. a | page 20 of 40 differential input configurations there are several ways to drive the ad9681 , either actively or passively. however, optimum performance is achieved by driving the analog inputs differentially. using a differential double balun configuration to drive the ad9681 provides excellent performance and a flexible interface to the adc (see figure 38) for baseband applications. similarly, differential transformer coupling also provides excellent performance (see figure 39). because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9681 , use of these passive configurations is recommended wherever possible. regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is recommended that the ad9681 inputs not be driven single- ended. voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9681 . configure vref using either the internal 1.0 v reference or an externally applied 1.0 v reference voltage. the various reference modes are summarized in the internal reference connection section and the external reference operation section. bypass the vref pin to ground externally, using a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the ad9681 detects the potential at the sense pin and configures the reference into two possible modes, which are summarized in table 9. if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 37), setting vref to 1.0 v. table 9. reference configuration summary selected mode sense voltage (v) resulting vref (v) resulting differential span (v p-p) fixed internal reference gnd to 0.2 1.0 internal 2.0 fixed external reference avdd 1.0 applied to external vref pin 2.0 vref sense 0.5v adc select logic 0.1f 1.0f vin?a/vin?b vin+a/vin+b adc core 11537-060 figure 37. internal reference configuration adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200 ? 33? 33 ? 33 ? et1-1-i3 c c 5pf r *c1 is optional 11537-059 vin?x1, vin?x2 vin+x1, vin+x2 figure 38. differential double balun input configuration for base band applications 2v p-p r r *c1 *c1 is optional 49.9 ? 0.1 f a dt1-1wt 1:1 z ratio adc *c1 c vcm 33? 33? 200 ? 0.1f 5pf 11537-056 vin?x1, vin?x2 vin+x1, vin+x2 figure 39. differential transformer coupled configuration for baseband applications
data sheet ad9681 rev. a | page 21 of 40 if the internal reference of the ad9681 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 40 shows how the internal reference voltage is affected by loading. 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 03.0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) internal v ref = 1v 11537-061 figure 40. v ref error vs. load current external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 41 shows the typical drift characteristics of the internal reference in 1.0 v mode. 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 11537-062 figure 41. typical v ref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7.5 k load (see figure 34). the internal buffer generates the positive and negative full-scale references for the adc core. there- fore, limit the external reference to a maximum of 1.0 v. do not leave the sense pin floating. clock input considerations for optimum performance, clock the ad9681 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 28) and require no external bias. clock input options the ad9681 has a flexible clock input structure. the clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the utmost concern, as described in the jitter considerations section. figure 42 and figure 43 show two preferred methods for clocking the ad9681 (at clock rates of up to 1 ghz prior to the internal clock divider). a low jitter clock source is converted from a single- ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies from 125 mhz to 1 ghz, and the rf transformer is recommended for clock frequencies from 10 mhz to 200 mhz. the antiparallel schottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9681 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9681 while preserving the fast rise and fall times of the signal that are critical to achieving a low jitter performance. however, the diode capaci- tance comes into play at frequencies above 500 mhz. take care when choosing the appropriate signal limiting diode. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 11537-064 figure 42. transformer coupled differential clock (up to 200 mhz) 0.1f 0.1f 0.1f clock input 0.1f 50? clk? clk+ schottky diodes: hsms2822 adc 11537-065 figure 43. balun coupled differential clock (up to 1 ghz)
ad9681 data sheet rev. a | page 22 of 40 if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 44. the ad9510/ ad9511 / ad9512 / ad9513/ ad9514 / ad9515-x / ad9516-x / ad9517-x clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? 50k ? 50k ? clk? clk+ clock input clock input adc ad951x pecl driver 11537-066 figure 44. differential pecl sample clock (up to 1 ghz) a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 45. the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515-x / ad9516-x / ad9517-x clock drivers offer excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 50k ? 50k ? clk? clk+ adc clock input clock input ad951x lvds driver 11537-067 figure 45. differential lvds sample clock (up to 1 ghz) in some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 v cmos signal. in such applications, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 46). optional 100? 0.1f 0.1f 0.1f 50? 1 1 50? resistor is optional. clk? clk+ adc v cc 1k? 1k? c lock input ad951x cmos driver 11537-068 figure 46. single-ended 1.8 v cm os input clock (up to 200 mhz) input clock divider the ad9681 contains an input clock divider with the ability to divide the input clock by integer values from 1 to 8. the ad9681 clock divider can be synchronized using the external sync input. bit 0 and bit 1 of register 0x109 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync causes the clock divider to reset to its initial state. this synchro- nization feature allows the clock dividers of multiple devices to be aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9681 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the per- formance of the ad9681 . noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs turned on. jitter on the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal.
data sheet ad9681 rev. a | page 23 of 40 jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) that is due only to aperture jitter (t j ) is expressed by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? ?? j a tf ? 2 1 in this equation, the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 47). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 11537-070 figure 47. ideal snr vs. input frequency and jitter treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9681 . separate the clock driver power supplies from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators are excellent clock sources. if another type of source generates the clock (by gating, dividing, or another method), ensure that it is retimed by the original clock at the last step. see the an-501 application note , aperture uncertainty and adc system performance , and the an-756 application note , sampled systems and the effects of clock phase noise and jitter , for more in depth information about jitter performance as it relates to adcs. power dissipation an d power-down mode as shown in figure 48, the power dissipated by the ad9681 is proportional to its sample rate and can be set to one of several power saving modes using register 0x100, bits[2:0]. 0.9 0.8 0.7 0.6 0.5 0.4 0.3 10 130 total power (w) sample rate (msps) 30 50 70 90 110 50msps setting 80msps setting 125msps setting 40msps setting 20msps setting 65msps setting 105msps setting 11537-071 figure 48. total power vs. f sample for f in = 9.7 mhz the ad9681 is placed in power-down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 2 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9681 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. the internal capacitors are discharged when the device enters power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map section for more details on using these features.
ad9681 data sheet rev. a | page 24 of 40 digital outputs and timing the ad9681 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p-p differential) at the receiver. when operating in reduced range mode, the output current reduces to 2 ma. this results in a 200 mv swing (or 400 mv p-p differential) across a 100 termination at the receiver. the ad9681 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as near to the receiver as possible. if there is no far end receiver termination or there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recom- mended that the trace length be less than 24 inches, with all traces the same length. place the differential output traces as near to each other as possible. an example of the fco and data stream with proper trace length and position is shown in figure 49. figure 50 shows an lvds output timing example in reduced range mode. d0 500mv/div d1 500mv/div dco 500mv/div fco 500mv/div 4ns/div 11537-074 figure 49. lvds output timing ex ample in ansi-644 mode (default) d0 400mv/div d1 400mv/div dco 400mv/div fco 400mv/div 4ns/div 11537-083 figure 50. lvds output timing example in reduced range mode
data sheet ad9681 rev. a | page 25 of 40 figure 51 shows an example of the lvds output using the ansi-644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on standard fr-4 material. figure 52 shows an example of trace lengths exceeding 24 inches on standard fr-4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. 6k 7k 1k 2k 3k 5k 4k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps tie jitter histogram (hits) 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns 0.8ns eye diagram voltage (mv) eye: all bits uls: 7000/400354 11537-075 figure 51. data eye for lvds outputs in ansi-644 mode with trace lengths of less than 24 inches on standard fr-4 material, external 100 far end termination only it is the responsibility of the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of all eight outputs to drive longer trace lengths, which can be achieved by program- ming register 0x15. although this option produces sharper rise and fall times on the data edges and is less prone to bit errors, it also increases the power dissipation of the drvdd supply. 500 400 300 200 100 ?500 ?400 ?300 ?200 ?100 0 ?0.8ns ?0.4ns 0ns 0.4ns ?0.8ns eye diagram voltage (mv) eye: all bits uls: 8000/414024 10k 12k 2k 4k 6k 8k 0k ?800ps ?600ps ?400ps ?200ps 0ps 200ps 400ps 600ps tie jitter histogram (hits) 11537-076 figure 52. data eye for lvds outputs in ansi-644 mode with trace lengths of greater than 24 inches on standard fr-4 material, external 100 far end termination only the default format of the output data is twos complement. table 10 shows an example of the output coding format. to change the output data format to offset binary, see the memory map section, register 0x14, bit[0]. table 10. digital output coding input (v) condition (v) offset binary output mode twos complement mode vin+ ? vin? +vref ? 0.5 lsb 1111 1111 1111 1100 0111 1111 1111 1100
ad9681 data sheet rev. a | page 26 of 40 data from each adc is serialized and provided on a separate channel in two lanes in ddr mode. the data rate for each serial stream is equal to 16 bits times the sample clock rate, with a maximum of 500 mbps/lane [(16 bits 125 msps)/(2 2) = 500 mbps/lane)]. the lowest typical conversion rate is 10 msps. see the memory map section for details on enabling this feature. two output clock types are provided to assist in capturing data from the ad9681 . dco1 and dco2 are used to clock the output data and their frequency is equal to 4 the sample clock (clk) rate for the default mode of operation. data is clocked out of the ad9681 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. dco1 is used to capture the d0x1/d1x1 (bank 1) data; dco2 is used to capture the d0x2/d1x2 (bank 2) data. fco1 and fco2 signal the start of a new output byte and toggle at a rate equal to the sample clock rate in 1 frame mode. fco1 frames the d0x1/d1x1 (bank 1) data and fco2 frames the d0x2/ d1x2 (bank 2) data. see the timing diagrams section for more information. when the spi is used, the dco phase can be adjusted in 60 increments relative to one data cycle (30 relative to one dco cycle). this enables the user to refine system timing margins if required. the default dco1 and dco2 to output data edge timing, as shown in figure 3, is 180 relative to one data cycle (90 relative to one dco cycle). a 12-bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower resolution systems. when changing the resolution to a 12-bit serial stream, the data stream is shortened. see figure 4 for the 12-bit example. however, in the default option with the serial output number of bits at 16, the data stream stuffs two 0s at the end of the 14-bit serial data. in default mode, as shown in figure 3, the msb is first in the data output serial stream. this can be inverted so that the lsb is first in the data output serial stream by using the spi. there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing (see table 11 for the output bit sequencing options that are available). some test patterns have two serial sequential words and can alternate in various ways, depending on the test pattern chosen. note that some patterns do not adhere to the data format select option. in addition, custom user defined test patterns can be assigned in register 0x19, register 0x1a, register 0x1b, and register 0x1c. table 11. flexible output test modes output test mode bit sequence (reg. 0x0d) pattern name digital output word 1 1 digital output word 2 1 subject to data format select 1 notes 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) n/a yes offset binary code shown 0010 +full-scale short 1111 1111 1111 (12-bit) 0000 0000 0000 0000 (16-bit) n/a yes offset binary code shown 0011 ?full-scale short 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16-bit) n/a yes offset binary code shown 0100 checkerboard 1010 1010 1010 (12-bit) 1010 1010 1010 1010 (16-bit) 0101 0101 0101 (12-bit) 0101 0101 0101 0100 (16-bit) no 0101 pn sequence long 2 n/a n/a yes pn23 itu 0.150 x 23 + x 18 + 1 0110 pn sequence short 2 n/a n/a yes pn9 itu 0.150 x 9 + x 5 + 1 0111 one-/zero-word toggle 1111 1111 1111 (12-bit) 111 1111 1111 1100 (16-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 0000 (16- bit) no 1000 user input register 0x19 to register 0x1a register 0x1b to register 0x1c no 1001 1-/0-bit toggle 1010 1010 1010 (12-bit) 1010 1010 1010 1000 (16-bit) n/a no 1010 1 sync 0000 0011 1111 (12-bit) 0000 0001 1111 1100 (16-bit) n/a no 1011 one bit high 1000 0000 0000 (12-bit) 1000 0000 0000 0000 (16-bit) n/a no pattern associated with the external pin 1100 mixed bit frequency 1010 0011 0011 (12-bit) 1010 0001 1001 1100 (16-bit) n/a no 1 n/a means not applicable. 2 all test mode options except pn sequence short and pn sequence long can support 12-bit to 16-bit word lengths to verify data c apture to the receiver.
data sheet ad9681 rev. a | page 27 of 40 the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. refer to section 5.1 of the itu-t 0.150 (05/96) standard for a descrip- tion of the pn sequence and how it is generated. the seed value is all 1s (see table 12 for the initial values). the output is a parallel representation of the serial pn9 sequence in msb-first format. the first output word is the first 14 bits of the pn9 sequence in msb aligned form. table 12. pn sequence sequence initial value next three output samples (msb first) twos complement pn sequence short 0x7f80 0x77c4, 0xf320, 0xa538 pn sequence long 0x7ffc 0x7f80, 0x8004, 0x7000 the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. refer to section 5.6 of the itu-t 0.150 (05/96) standard for a description of the pn sequence and how it is generated. the seed value is all 1s (see table 12 for the initial values), and the ad9681 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb-first format. the first output word is the first 14 bits of the pn23 sequence in msb aligned format. consult the memory map section for information on how to change these additional digital output timing features through the spi. sdio/olm pin for applications that do not require spi mode operation, the csb1 and csb2 pins are tied to avdd, and the sdio/olm pin controls the output lane mode according to table 13. for applications where the sdio/olm pin is not used, tie csb1 and csb2 to avdd. when using the one-lane mode, use an encode rate of 62.5 msps to meet the maximum output rate of 1 gbps. table 13. output lane mode pin settings output lane mode voltage (sdio/olm pin) output mode avdd (default) two-lane. 1 fr ame, 16-bit serial output. gnd one-lane. 1 frame, 16-bit serial output. sclk/dtp pin the sclk/dtp pin can enable a single digital test pattern if it and the csb1 and csb2 pins are held high during device power-up. when sclk/dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000 0000. the fco1, fco2, dco1, and dco2 pins function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignment adjustments among the fco1, fco2, dco1, dco2, and output data. the sclk/dtp pin has an internal 30 k resistor to gnd and can be left unconnected for normal operation. table 14. digital test pattern pin settings selected digital test pattern dtp voltage resulting d0xx and d1xx normal operation no connect normal operation dtp avdd 1000 0000 0000 0000 additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about the options available. csb1 and csb2 pins tie the csb1 and csb2 pins to avdd for applications that do not require spi mode operation. tying csb1 and csb2 high causes all sclk and sdio spi communication information to be ignored. csb1 selects/deselects spi circuitry affecting the d0x1/d1x1 outputs (bank 1). csb2 selects/deselects spi circuitry affecting the d0x2/d1x2 (bank 2) outputs. it is recommended that csb1 and csb2 be controlled with the same signal; that is, tie them together. in this way, whether tying them to avdd or selecting spi functionality, both banks of adcs are controlled identically and are always in the same state. rbias1 and rbias2 pins to set the internal core bias current of the adc, place a 10.0 k, 1% tolerance resistor to ground at each of the rbias1 and rbias2 pins. output test modes the ad9681 includes a built-in test feature designed to enable verification of the integrity of each data output channel, as well as to facilitate board level debugging. various output test modes are provided to place predictable values on the outputs of the ad9681. the output test modes are described in table 11 and controlled by the output test mode bits at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an-877 application note , interfacing to high speed adcs via spi .
ad9681 data sheet rev. a | page 28 of 40 serial port interface (spi) the ad9681 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi offers the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for general operational information, see the an-877 application note , interfacing to high speed adcs via spi . spi information specific to the ad9681 is found in the ad9681 datasheet and takes precedence over the general information found in the an-877 application note. configuration using the spi four pins define the spi of this adc: the sclk/dtp pin (sclk functionality), the sdio/olm pin (sdio functionality) and the csb1 and csb2 pins (see table 15). sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. sdio (serial data input/output) serves a dual function, allowing data to be sent to and read from the internal adc memory map registers. csb1 and csb2 (chip select bar) are active low controls that enable or disable the read and write cycles. table 15. serial port interface pins pin function sclk (sclk/dtp) serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio (sdio/olm) serial data inp ut/output. a dual-purpose pin that serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb1, csb2 chip select bar. an active low control that gates the read and write cycles. csb1 enables/disables the spi for four channels in bank 1; csb2 enables/ disables the spi for four channels in bank 2. the falling edge of csb1 and/or csb2, in conjunction with the rising edge of sclk, determines the start of the framing. for an example of the serial timing and its definitions, see figure 53 and table 5. other modes involving the csb1 and csb2 pins are available. to permanently enable the device, hold csb1 and csb2 low indefinitely; this is called streaming. csb1 and csb2 can stall high between bytes to allow additional external timing. tie csb1 and csb2 high to place spi functions in high impedance mode. this mode turns on any spi secondary pin functions. it is recommended that csb1 and csb2 be controlled with the same signal by tying them together. in this way, whether tying them to avdd or selecting spi functionality, both banks of adcs are controlled identically and are always in the same state. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to both program the chip and read the contents of the on-chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. input data registers on the rising edge of sclk, and output data transmits on the falling edge. after the address information passes to the converter requesting a read, the sdio line transitions from an input to an output within 1/2 of a clock cycle. this timing ensures that when the falling edge of the next clock cycle occurs, data can be safely placed on this serial line for the controller to read. all data is composed of 8-bit words. data can be sent in msb- first mode or in lsb-first mode. msb-first mode is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csbx t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 11537-078 figure 53. serial port interface timing diagram
data sheet ad9681 rev. a | page 29 of 40 hardware interface the pins described in table 15 comprise the physical interface between the user programming device and the serial port of the ad9681 . the sclk/dtp pin (sclk functionality) and the csb1 and csb2 pins function as inputs when using the spi interface. the sdio/olm pin (sdio functionality) is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note , micro- controller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb1 and csb2 signals, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9681 to prevent these signals from transitioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power-on, they serve a specific function. table 13 and table 14 describe the strappable functions that are supported on the ad9681. configuration without the spi in applications that do not interface to the spi control registers, the sdio/olm pin, the sclk/dtp pin, and the pdwn pin serve as standalone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for output lane mode control, digital test pattern control, and power-down feature control. in this mode, connect csb1 and csb2 to avdd, which disables the serial port interface. when the device is in spi mode, the pdwn pin (if enabled) remains active. for spi control of power-down, set the pdwn pin to its inactive state (low). spi accessible features table 16 provides a brief description of the general features that are accessible via the spi. these features are described further in the an-877 application note , interfacing to high speed adcs via spi . the ad9681 device-specific features are described in detail in the memory map register descriptions section following table 17, the external memory map register table. table 16. features accessible using the spi feature name description power mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync function offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity adc resolution allows scalable power consumption options with respect to the sample rate
ad9681 data sheet rev. a | page 30 of 40 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is divided into three sections: the chip confi- guration registers (address 0x00 to address 0x02); the device index and transfer registers (address 0x05 and address 0xff); and the global adc function registers, including setup, control, and test (address 0x08 to address 0x109). the memory map register table (see table 17) lists the default hexadecimal value for each hexadecimal address shown. the column with the bit 7 (msb) heading is the start of the default hexadecimal value given. for example, address 0x05, the device index register, has a hexadecimal default value of 0x3f. this means that in address 0x05, bits[7:6] = 0, and the remaining bits, bits[5:0], = 1. this setting is the default channel index setting. the default value results in all specified adc channels receiving the next write command. for more information on this function and others, see the an-877 application note , interfacing to high speed adcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are not listed in table 17 are not currently supported for this device. write the unused bits of a valid address location with 0s. writing to these locations is required only when some of the bits of an address location are valid (for example, address 0x05). do not write to an address location if the entire address location is open or if the address is not listed in table 17 (for example, address 0x13). default values after the ad9681 is reset (via bit 5 and bit 2 of address 0x00), the registers are loaded with default values. the default values for the registers are listed in the default value (hex) column of table 17, the memory map register table. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel specific registers some channel setup functions can be programmed independently for each channel. in such cases, channel address locations are internally duplicated for each channel; that is, each channel has its own set of registers. these registers and bits are designated in table 17 as local. access these local registers and bits by setting the appropriate data channel bits (a1, a2 through d1, d2) and the clock channel bits (dco1, dco2 and fco1, fco2), found in register 0x05. if all the valid bits are set in register 0x05, the subsequent write to a local register affects the registers of all the data channels and the dcox/fcox clock channels. in a read cycle, set only one channel (a1, a2 through d1, d2) to read one local register. if all the bits are set during a spi read cycle, the device returns the value for channel a1. registers and bits that are designated as global in table 17 are applicable to the channel features for which independent settings are not allowed; thus, they affect the entire device. the settings in register 0x05 do not affect the global registers and bits.
data sheet ad9681 rev. a | page 31 of 40 memory map the ad9681 uses a 3-wire (bidirectional sdio) interface and 16-bit addressing. therefore, bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when bit 5 in register 0x00 is set high, the spi enters a soft reset where all of the user re gisters revert to their default values and bit 2 is automatically cleared. table 17. memory map register table reg. addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configuration registers 0x00 spi port configuration 0 = sdio active lsb first soft reset 1 = 16-bit address 1 = 16-bit address soft reset lsb first 0 = sdio active 0x18 nibbles are mirrored such that a given register value yields the same function for either lsb-first mode or msb- first mode. the default for adcs is 16-bit mode. 0x01 chip id (global) 8-bit chip id, bits[7:0]; 0x8f = the ad9681 , an octal, 14-bit, 125 msps serial lvds 0x8f unique chip id used to differ- entiate devices. read only. 0x02 chip grade (global) open speed grade id, bits[6:4]; 110 = 125 msps open open open open read only unique speed grade id used to differentiate graded devices. read only. device index and transfer registers 0x05 device index open open dco1, dco2 clock channels fco1, fco2 clock channels d1, d2 data channels c1, c2 data channels b1, b2 data channels a1, a2 data channels 0x3f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0xff transfer open open open open open open open initiate override 0x00 sets resolution/ sample rate override. global adc function registers 0x08 power modes (global) open open external power- down pin function; 0 = full power- down, 1 = standby open open open internal power-down mode, bits[1:0]; 00 = chip run 01 = full power-down 10 = standby 11 = digital reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open open open open open open open duty cycle stabilizer; 0 = off 1 = on 0x01 turns duty cycle stabilizer on or off. 0x0b clock divide (global) open open open open open clock di vide ratio, bits[2:0]; 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 divide ratio is the value plus 1.
ad9681 data sheet rev. a | page 32 of 40 reg. addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0c enhancement control open open open open open chop mode; 0 = off 1 = on open open 0x00 enables/ disables chop mode. 0x0d test mode (local except for pn sequence resets) user input test mode, bits[7:6]; 00 = single 01 = alternate 10 = single once 11 = alternate once (affects user input test mode only; register 0x0d, bits[3:0] = 1000) reset pn long gen reset pn short gen output test mode, bits[3:0] (local); 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn23 sequence 0110 = pn9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, test data is placed on the output pins in place of normal data. 0x10 offset adjust (local) 8-bit device offset adjustment, bits[7:0] (local); offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 device offset trim. 0x14 output mode open lvds-ansi/ lvds-ieee option; 0 = lvds- ansi 1 = lvds- ieee reduced range link (global); see table 18 open open open output invert; 0 = not inverted 1 = inverted (local) open output format; 0 = offset binary 1 = twos comple- ment (default) (global) 0x01 configures outputs and format of the data. 0x15 output adjust open open output driver termination, bits[5:4]; 00 = none 01 = 200 10 = 100 11 = 100 open open open fcox, dcox output drive (local); 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input cl ock phase adjust, bits[6:4]; (value is number of input clock cycles of phase delay; see table 19) output clock phase adjust, bits[3:0]; (0000 to 1011; see table 20) 0x03 on devices that use global clock divide, determines which phase of the divider output supplies the output clock. internal latching is unaffected. 0x18 v ref open open open open open input full-scale adjustment; digital scheme, bits[2:0]; 000 = 1.0 v p-p 001 = 1.14 v p-p 010 = 1.33 v p-p 011 = 1.6 v p-p 100 = 2.0 v p-p 0x04 digital adjust- ment of input full-scale voltage. does not affect analog voltage reference. 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_msb (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb.
data sheet ad9681 rev. a | page 33 of 40 reg. addr. (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x21 serial output data control (global) lvds output lsb first sdr/ddr one-lane/two-lane, wordwise/bitwise/byt ewise, bits[6:4]; 000 = sdr two-lane, bitwise 001 = sdr two-lane, bytewise 010 = ddr two-lane, bitwise 011 = ddr two-lane, bytewise 100 = ddr one-lane, wordwise pll low encode rate mode select 2 frame serial output number of bits, bits[1:0]; 00 = 16 bits 10 = 12 bits 0x30 serial stream control. default causes msb first and the native bit stream. 0x22 serial channel status (local) open open open open open open channel output reset channel power- down 0x00 powers down individual sections of a converter. 0x100 resolution/sample rate override open resolution/ sample rate override enable resolution, bits[5:4]; 01 = 14 bits 10 = 12 bits open sample rate, bits[2:0]; 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 101 = 105 msps 110 = 125 msps 0x00 resolution/ sample rate override (requires transfer register, register 0xff). 0x101 user i/o control 2 ope n open open open open open open sdio pull- down 0x00 disables sdio pull-down. 0x102 user i/o control 3 open open open open vcm power- down open open open 0x 00 vcm control. 0x109 sync open open open open open open sync next only enable sync 0x00
ad9681 data sheet rev. a | page 34 of 40 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an-877 application note , interfacing to high speed adcs via spi . device index (register 0x05) there are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context), regardless of which are selected. bits[3:0] in register 0x05 select which individual data channels are affected. the output clock channels are selected in register 0x05 as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 = 1 in the transfer register initializes the settings in the adc resolution/sample rate override register (address 0x100). power modes (register 0x08) bits[7:6]open bit 5external power-down pin function when set (bit 5 = 1), the external pdwn pin initiates standby mode. when cleared (bit 5 = 0), the external pdwn pin initiates full power-down mode. bits[4:2]open bits[1:0]internal power-down mode in normal operation (bits[1:0] = 00), all adc channels are active. in full power-down mode (bits[1:0] = 01), the digital datapath clocks are disabled and the digital datapath is reset. outputs are disabled. in standby mode (bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the spi port. note that the spi is always left under control of the user; that is, it is never automatically disabled or in reset (except by power-on reset). enhancement control (register 0x0c) bits[7:3]open bit 2chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad9681 is a feature that can be enabled by setting bit 2 = 1. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2, where they can be filtered. bits[1:0]open output mode (register 0x14) bit 7open bit 6lvds-ansi/lvds-ieee option setting bit 6 = 1 chooses the lvds-ieee (reduced range) option. (the default setting is lvds-ansi.) as described in table 18, when either lvds-ansi mode or the lvds-ieee reduced range link is selected, the user can select the driver termination resistor in register 0x15, bits[5:4]. the driver current is automatically selected to give the proper output swing. table 18. lvds-ansi/lvds-ieee options lvds-ansi/ lvds-ieee option, bit 6 output mode output driver termination output driver current 0 lvds-ansi user selectable automatically selected to give proper swing 1 lvds-ieee reduced range link user selectable automatically selected to give proper swing bits[5:3]open bit 2output invert setting bit 2 = 1 inverts the output bit stream. bit 1open bit 0output format by default, setting bit 0 = 1 sends the data output in twos complement format. clearing this bit (bit 0 = 0) changes the output mode to offset binary. output adjust (register 0x15) bits[7:6]open bits[5:4]output driver termination these bits allow the user to select the internal output driver termination resistor. bits[3:1]open bit 0fcox, dcox output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco1, fco2, dco1, and dco2 outputs only. the default value (bit 0 = 0) sets the drive to 1. increase the drive to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0 = 1. these features cannot be used with the output driver termination selected. the termination selection takes precedence over the 2 driver strength on fco1, fco2, dco1, and dco2 when both the output driver termination and output drive are selected.
data sheet ad9681 rev. a | page 35 of 40 output phase (register 0x16) bit 7open bits[6:4]input clock phase adjust when the clock divider (register 0x0b) is used, the applied clock is at a higher frequency than the internal sampling clock. bits[6:4] determine at which phase of the external clock the sampling occurs. this is applicable only when the clock divider is used. it is prohibited to select a value for bits[6:4] that is greater than the value of bits[2:0], register 0x0b. see table 19 for more information. table 19. input clock phase adjust options input clock phase adjust, bits[6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[3:0]output clock phase adjust see table 20 for more information. table 20. output clock phase adjust options output clock phase adjust, bits[3:0] dco phase adjustment (degrees relative to d0x/d1x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 serial output data control (register 0x21) the serial output data control register programs the ad9681 in various output data modes, depending on the data capture solution. table 21 describes the various serialization options available in the ad9681. resolution/sample rate ov erride (register 0x100) this register is designed to allow the user to downgrade the device (that is, establish lower power) for applications that do not require full sample rate. settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is set to 1. this function does not affect the sample rate; it affects the maximum sample rate capability of the adc, as well as the resolution. user i/o control 2 (register 0x101) bits[7:1]open bit 0sdio pull-down set bit 0 = 1 to disable the internal 30 k pull-down on the sdio/olm pin. this feature limits loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4]open bit 3vcm power-down set bit 3 = 1 to power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0]open
ad9681 data sheet rev. a | page 36 of 40 table 21. spi register options register 0x21 contents serialization options selected dco multiplier timing diagram serial output number of bits (sonb) frame mode serial data mode 0x30 16-bit 1 ddr two-lane, bytewise 4 f s figure 3 (default setting) 0x20 16-bit 1 ddr two-lane, bitwise 4 f s figure 3 0x10 16-bit 1 sdr two-lane, bytewise 8 f s figure 3 0x00 16-bit 1 sdr two-lane, bitwise 8 f s figure 3 0x34 16-bit 2 ddr two-lane, bytewise 4 f s figure 5 0x24 16-bit 2 ddr two-lane, bitwise 4 f s figure 5 0x14 16-bit 2 sdr two-lane, bytewise 8 f s figure 5 0x04 16-bit 2 sdr two-lane, bitwise 8 f s figure 5 0x40 16-bit 1 ddr one-lane, wordwise 8 f s figure 7 0x32 12-bit 1 ddr two-lane, bytewise 3 f s figure 4 0x22 12-bit 1 ddr two-lane, bitwise 3 f s figure 4 0x12 12-bit 1 sdr two-lane, bytewise 6 f s figure 4 0x02 12-bit 1 sdr two-lane, bitwise 6 f s figure 4 0x36 12-bit 2 ddr two-lane, bytewise 3 f s figure 6 0x26 12-bit 2 ddr two-lane, bitwise 3 f s figure 6 0x16 12-bit 2 sdr two-lane, bytewise 6 f s figure 6 0x06 12-bit 2 sdr two-lane, bitwise 6 f s figure 6 0x42 12-bit 1 ddr one-lane, wordwise 6 f s figure 8
data sheet ad9681 rev. a | page 37 of 40 applications information design guidelines before starting the design and layout of the ad9681 as a system, it is recommended that the designer become familiar with these guidelines, which describe the special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the ad9681 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd, use several different decoupling capacitors for both high and low frequencies. place these capacitors near the point of entry at the pcb level and near the pins of the device, with minimal trace length. a single pcb ground plane is typically sufficient when using the ad9681 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. board layout considerations for optimal performance, give special consideration to the ad9681 board layout. the high channel count and small foot- print of the ad9681 create a dense configuration that must be managed for matters relating to crosstalk and switching noise. sources of coupling trace pairs interfere with each other by inductive coupling and capacitive coupling. use the following guidelines: ? inductive coupling is current induced in a trace by a changing magnetic field from an adjacent trace, caused by its changing current flow. mitigate this effect by making traces orthogonal to each other whenever possible and by increasing the distance between them. ? capacitive coupling is charge induced in a trace by the changing electric field of an adjacent trace. this effect can be mitigated by minimizing facing areas, increasing the distance between traces, or changing dielectric properties. ? through-vias are particularly good conduits for both types of coupling and must be used carefully. ? adjacent trace runs on the same layer may cause unbalanced coupling between channels. ? traces on one layer should be separated by a plane (ac ground) from the traces on another layer. significant coupling occurs through gaps in that plane, such as the setback around through-vias. crosstalk between inputs to avoid crosstalk between inputs, consider the following guidelines: ? when routing inputs, sequentially alternate input channels on the top and bottom (or other layer) of the board. ? ensure that the top channels have no vias within 5 mm of any other input channel via. ? for bottom channels, use a via-in-pad to minimize top- metal coupling between channels. ? avoid running input traces parallel with each other that are nearer than 2 mm apart. ? when possible, lay out traces orthogonal to each other and to any other traces that are not dc. ? secondhand or indirect coupling may occur through nonrelated dc traces that bridge the distance between two traces or vias. coupling of digital output switching noise to analog inputs and clock to avoid the coupling of digital output switching noise to the analog inputs and the clock, use the following guidelines: ? vias on the outputs are a main conduit of noise to the vias on the inputs. maintain 5 mm of separation between any output via and any input via. ? place the encode clock traces on the top surface. vias are not recommended in the clock traces. however, if they are required, ensure that there are no clock trace vias within 5 mm of any input via or output via. ? place output surface traces (not imbedded between planes) orthogonal to one another as much as possible. avoid parallel output to input traces within 2 mm. ? route digital output traces away from the analog input side of the board. ? coupling among outputs is not a critical issue, but separation between these high speed output pairs increases the noise margin of the signals and is good practice.
ad9681 data sheet rev. a | page 38 of 40 clock stability considerations when powered on, the ad9681 goes into an initialization phase where an internal state machine sets up the biases and the registers for proper operation. during the initialization process, the ad9681 needs a stable clock. if the adc clock source is not present or not stable during adc power-up, the state machine is disrupted and the adc starts up in an unknown state. to correct this, reinvoke an initialization sequence after the adc clock is stable by issuing a digital reset using register 0x08. in the default configuration (internal v ref , ac-coupled input) where v ref and v cm are supplied by the adc itself, a stable clock during power-up is sufficient. when v ref or v cm is supplied by an external source, it, too, must be stable at power-up. otherwise, a subsequent digital reset, using register 0x08, is needed. the pseudocode sequence for a digital reset follows: spi_write (0x08, 0x03); # digital reset spi_write (0x08, 0x00); # normal operation vcm decouple the vcmx pin to ground with a 0.1 f capacitor. reference decoupling decouple the vref pin externally to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port ensure that the spi port is inactive during periods when the full dynamic performance of the converter is required. because the sclk, csb1, csb2, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9681 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
data sheet ad9681 rev. a | page 39 of 40 outline dimensions compliant to jedec standards mo-275-eeab-1. 11-18-2011-a 0.80 0.60 ref a b c d e f g 9 10 8 1112 7 5 642 31 bottom view 8.80 sq h j k l m detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 1.70 max ball diameter seating plane 10.10 10.00 sq 9.90 a1 ball corner a1 ball corner 0.32 min 1.00 min figure 54. 144-ball chip scale package ball grid array [csp_bga] (bc-144-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9681bbcz-125 ?40c to +85c 144-ball chip scale package ball grid array [csp_bga] bc-144-7 AD9681BBCZRL7-125 ?40c to +85c 144-ball chip scale package ball grid array [csp_bga] bc-144-7 ad9681-125ebz evaluation board 1 z = rohs compliant part.
ad9681 data sheet rev. a | page 40 of 40 notes ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d11537-0-12/13(a)

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